The layout for large-scale integrated microchips is one of the most time consuming tasks in the design cycle for an integrated circuit (IC). One input to this design process is a partitioned circuit wherein elementary components of the circuit are grouped to build a number of macro cells. On the borders of these cells, signal trace endpoints or terminals are located to provide signal paths between circuit blocks of the IC and connection layers such as metal or polysilicon layers. These connection layers, also known as interconnects, require some finite width and thickness to ensure reliability of the interconnect and signal integrity.
The output of this design process is a layout for the integrated circuit. The layout describes the placement of the macro cells and the routes for the interconnects between the macro cells. One common objective in layout optimization is to find an arrangement that minimizes overall area. Cells are not allowed to overlap each other, and the routing has to meet specific technical constraints, i.e., space between parallel wires has to be added to prevent short circuits and transmission effects, and for some critical traces, the delay has to stay below a given threshold, which results in maximal admissible wire lengths for these traces.
One frequently occurring situation encountered in this design process is when a single source is used to generate identical or duplicate signals, e.g., clocks, currents, etc. that are to be supplied to multiple destinations. An example would be a biasing current that is being supplied to analog circuits. The distribution of these currents can be a significant challenge in situations where the analog circuits are macro-based and multiple distributions are to occur. This becomes even more difficult when the multiple analog circuits require independent biasing currents from the source. That is, while the source can readily produce independent biasing current for any number of analog macros, providing each current to each analog macro is problematic due to the fact that biasing currents are delicate and sensitive signals.
Frequently in the prior art custom routing is employed. This not only increases costs of design but invariable results in increased numbers of signal paths between blocks. When numerous signal paths are required between circuit blocks, the routing congestion caused by placement of the associated interconnects will increase the overall size of the IC and thus increase the cost of the product. That congestion has an increased effect when the area between the circuit blocks is limited. A further problem arises when numerous tightly spaced functional blocks require a high number of signal paths between these blocks. The associated numerous interconnects will cause even more IC area congestion that will further increase the IC size and associated cost.